Multigate field-effect transistor (MuGFET) or fin field-effect transistor (FinFET) devices are expected to be used in the future due to the limited down-scaling capability of conventional planar or bulk CMOS technologies (CMOS: complementary metal oxide semiconductor). A fin field-effect transistor (FinFET) may be understood to mean a field-effect transistor having at least one fin structure. A fin structure or fin may, for example, include a ridge structure or a bridge structure, which is formed or freely suspended on a substrate. A multi-gate field effect-transistor (MuGFET) may, for example, include a field-effect transistor, in which a channel region is driven by two or more gates, e.g. a MOS device that has multiple gates on one fin.
FinFET devices are typically designed for high-speed logic core applications featuring low supply voltages (e.g., 0.8 V to 1.2 V). A reduction of source/drain series resistance is one issue to be addressed in FinFET technology optimization. In this context, a possible process solution may be Selective Epitaxial Growth (SEG) of silicon.
In SEG, silicon may be grown on the surface of an existing silicon film (so-called “seed silicon”). The silicon therefore may grow outside of the channel/spacer region on top of the source/drain landing pads of a FinFET device, on top of the fins (where not covered by the gate), and may (partially or fully) close the spacings between the fins (typically in facets). No SEG silicon will be grown on isolating layers such as buried oxide or nitride.
SEG may be an expense factor in the processing and may account, for example, for up to 4% of the total wafer processing cost. One reason for this may be seen in the slow growth rate of an SEG layer. For example, a regular SEG layer thickness as applied for source/drain resistance reduction may typically be on the order of about 10 nm to 60 nm. A thinner SEG layer having, for example, a thickness of about 5 nm to 10 nm, may add only about 1% of processing cost.
BiCMOS technologies integrate both CMOS and bipolar components into one processing technology which may be applied for mixed signal applications, such as high power and or high frequency circuits, where intelligent, complex and fast logic may be needed at the same time.
For a large market penetration and for covering various applications, FinFET technologies may need to cover a variety of additional device classes that expand beyond pure logic MOS devices. Integrating, for example, analog radio-frequency (RF) and mixed signal circuits into a FinFET technology may also require bipolar transistors for high power applications and fast switching behavior.
One further aspect may be the need for devices that are robust against damage by electrostatic discharge (ESD). Particularly in light of the known ESD sensitivity of conventional silicon-on-insulator (SOI) technologies, it may be desirable to protect output drivers and any other parts including power supply lines in such advanced technologies against ESD damage. In this context, ESD protection devices may be used to safely shunt the energy of an ESD pulse without being damaged themselves. Bipolar transistor operation is used frequently in case of mixed-voltage/over-voltage tolerant circuit applications where local clamping devices are used.